- The amount of clock cycles between an active command row address strobe (RAS) and a CAS is measured in tRCD. It's the period between the memory controller claiming a row address and the succeeding read or write instruction asserting a column address. Row address to column address delay time is denoted by tRCD.
- The number of clock cycles taken to open a row and access a column is measured in tRCD. tRCD + CL are additional delays introduced by reading the initial bit of memory from a DRAM without any active rows
- tRCD is the time it takes the RAM to get to the new address in the shortest possible time.
Read More: What Is Ecc Memory?
