While chips have historically been packaged with a single silicon tile inside, companies like Intel are starting to stack several of them, occasionally combining different technologies, to improve performance as the industry struggles to make features on these tiles smaller and smaller so that they can fit more computing power into them.

On Monday, Siemens Digital Industries Software, a division of Siemens AG, announced the release of Tessent Multi-die, new software that automates the design process for testing chips built with advanced packaging.

A new software system from Siemens Digital Industries Software has been released; it streamlines the design process for testing chips with multiple layers of silicon tiles.

The Tessent Multi-die software responds to the pattern of chip manufacturers stacking many tiles to enhance processing power and combining various technologies to improve performance. Prior to manufacture, the chips must include a port for testing.

Chips have always been packaged with a single silicon tile inside, but as the industry struggles to compress more computing power into ever-tinier features on these tiles, businesses like Intel are beginning to stack multiple of them, occasionally fusing various technologies.

Ankur Gupta, head of the Tessent division at Siemens, stated that up until now, Siemens has had to deal with customers on a case-by-case basis since evaluating these chips after they are created has been challenging due to the multiple layers of tiles.

The release of Tessent Multi-die, a new piece of software that automates the design process for testing chips created with sophisticated packaging, was announced by Siemens Digital Industries Software, a branch of Siemens AG, on Monday.

Traditionally, chips have only had a single silicon tile, but as the industry attempts to fit more computing power into ever-tinier features on these tiles, companies like Intel are starting to stack them up and occasionally combining different technologies.

A port for testing must be built into the chip before it is created because testing is an important step in the chip-making process.

We are currently automating the solution to make it available for broad usage by everyone, according to Gupta, who spoke to Reuters.

He claimed that simplifying the testing procedure for chips with advanced packaging, also known as 2.5 and 3-dimensional packaging, will contribute in the advancement of the new technology.