• Between the data request and the precharge command, tRAS is the minimum number of clock cycles required to access a specific row of data in RAM. The active to precharge delay is what it's called. The tRAS is the minimum number of clock cycles required between issuing a row active command and issuing the precharge command.
• It is also known as 'Activate to Precharge Delay' or 'Minimum RAS Active Time.' In SDRAM modules, this overlaps with the tRCD and is simply tRCD+CL. It is about tRCD+2xCL in other circumstances. tRAS calculates the minimum number of cycles a row needs remain open in order to write data correctly.

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